“The IBM innovation reflected in this new 2 nm chip is essential to the entire semiconductor and IT industry.”
In a major breakthrough, IBM announced the first of its kind 2nm chip based on nanosheet technology. The company said this chip would help advance the semiconductor industry and cater to its growing chip demand.
The 2nm processors can quadruple the battery life of cell phones. Based on average use, the phone battery could last up to four days. The chip offers 45 percent higher performance and uses 75 percent lower energy than today’s most advanced 7nm node chips.
The power/performance combination expedites the development and delivery of cutting-edge cognitive, edge and other computing platforms delivered via hybrid cloud environments and encryption accelerators built to operate with quantum computers.
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The 2nm nanotechnology can accommodate up to 50 billion transistors on a fingernail-sized chip. More transistors on a chip will enable designers to innovate for leading-edge workloads such as AI, cloud computing, hardware-enforced security, and encryption.
IBM’s new offering is still in the proof-of-concept phase and could be a while before it is available commercially. At the moment, IBM’s rival companies-Samsung and TSMC are producing 5nm chips in their foundries. TSMC had announced earlier that it will begin producing 4nm chips by the end of 2021 and will roll out 3nm chips by the second half of 2022. Intel’s 7nm chips is still in the works.
How did IBM get here?
The term nanosheet was first coined in the IBM labs in 2012 when its team of researchers worked on a new device architecture. The goal was to develop a suitable alternative to the popular nanowire structure. IBM’s Eureka moment came with the nanosheet architecture, which offered nanowire’s electrostatic benefits along with the density required for better performance.
With this combination of features, nanosheet overcame FinFET, a dominant transistor structure at the time. However, the industry was quickly moving past FinFET design. Designers tried cramming more transistors, but that resulted in transistor leakage.
FinFET technology derives its name from the FET structure and looks like a set of fins. In this structure, the electrons flow through thin vertical fins, instead of a flat surface, to pass through the transistors. On the other hand, the nanosheets stack transistors on top of each other to form layered structures.
IBM then decided to introduce a second iteration of the nanosheet transistor architecture, which involved a horizontally stacked GAA chip design. It has four gates that enable electric signals to transmit through and between the other transistors on a chip. The team realised that the inner spacer module in the transistor architecture could reduce gate to source/drain capacitance and improve nanosheet performance. In 2019, the team used a dry indent technique to develop a new inner spacer process. It helps in achieving an improved inner spacer profile.
The dry inner spacer process was combined with industry’s bottom dielectric isolation to create a 12nm gate length which is two dozen atoms long. This helps reduce sub-channel leakage, provides immunity to process variation, and improves power performance.
The team used extreme ultraviolet (EUV) lithography pattern to develop nanosheet devices ranging from 15 to 70nm width at the front-end-of-line (FEOL). FEOL is the first portion of the integrated circuit where transistors are patterned in a semiconductor.
The first 2nm transistor is the new multi-threshold-voltage (Multi-Vt) device with leakage levels spanning magnitudes of three orders. It allows manufacturers to choose a better level of performance.
IBM’s 5nm design
The innovation comes four years after IBM announced its 5nm design. IBM partnered with GlobalFoundries and Samsung as part of the research. Notably, IBM had sold its Microelectronics division to GlobalFoundries in 2014 and exited the chip foundry business.
Like the 2nm technology, the 5nm design also builds on Extreme Ultraviolet lithography to manufacture the nanosheet transistor design and the use of stacked silicon nanosheets to pack transistors closely.