Apple’s leap towards 3nm for M2 Pro and A17 chip for Mac and iPhones, respectively, seems within grasp now that TSMC has announced the expansion of its initial plans to set up 5nm production in Arizona to a second phase which will include 3nm. But, however, reality says otherwise, or rather reports vary, and they seem like blatant contradictions to each other. For instance, the latest DigiTimes report says that the production of 3nm is “unlikely to ramp up” until the enhanced version of the 3nm (N3E) gets underway.  

At the moment, Apple is using 4nm chips for its A16 bionic chip which, technically, is an enhancement of TSMC’s 5nm family. The N4P, as it is called, is an 11% performance boost over the original N5 (5nm) technology and a 6% boost over N4 (4nm). 

The cost of ‘unnatural’ scaling in the advanced node areas was evident when speculations rounded that the complex 3nm technology would result in TSMC missing their typical two-year cycle for newer process node releases. TSMC’s CEO Dr C. C. Wei quoted a three to four months delay in 3nm as compared with 5nm, citing complications in technology and customers’ product design. The customer Wei refers to here seems to be Apple, who accounts for 25% of TSMC’s revenue and is now “confirmed” by many sources to be the first in line to reap the benefits of the 3nm process. 

Moore’s Law Declining

The delay in 3nm chip production earlier led to Apple being forced to change its plans for its iPhones. Apple dropped its not-so-successful Mini model and replaced it with the Plus model which, instead of receiving the A16 (4nm) chipset, carried the existing A15 (5nm) bionic chip. Meanwhile, the flagship iPhone 14 Pro models are equipped with 6GB of LPDDR5 and the A16 chip. LPDDR5 is a low power volatile (DRAM) device memory standard defined for storage of code, apps and data. 

SemiAnalysis reported that the chip plus the RAM increase would be cost-prohibitive, resulting in more than a $40 increase in the bill of materials (BOM). Thus, sticking to an A15 chip for its non-Pro models enables Apple to maintain its price point, since rampantly increasing the prices would directly affect Apple’s sales volume. But, as is implicated before, even with the A16 chip using the N4 process, they are in the same node family as N5 and also share the same fabs. 

This means that, for the first time, Apple will share three generations of devices with the same process density. In addition, the report states that, while Apple’s CPU performance has slowed down, it will bring large core changes while also improving GPU, NPU, media blocks, and ISPs. Furthermore, increasing the memory bandwidth by stepping up to LPDDR5 also means that it will incur a large cost increase since the cost per bit of DRAM has not really fallen. 

Therefore, the production of 3nm is not entirely good news for Apple since they will have to face the reality of the rising costs of advanced chips again. On top of that, reports circulated that TSMC plans to raise the price of the 8-inch chip wafers by 6% while 12-inch wafers are set to increase by 3~5%. Although Apple initially refused the hike in price, it allegedly changed its mind later and agreed to the terms. 

5nm or 3nm—The better deal? 

In another report, SemiAnalysis said that many companies would look to stick to the N5 class process node for a long time to come. But, there will also be many others who will upgrade to N3, keeping all other IPs—such as SRAM and analogue—on older process technologies since the volume necessary to achieve a cost-per-transistor increase becomes higher and higher, delays become more challenging and respins become more expensive. 

However, the SRAM scaling issues resulted in relatively smaller cost benefits in Apple’s transition from 7nm to 5nm, making 2018 be the last year with significant increase in cost benefits for Apple owing to TSMC’s 10nm to 7nm process node shrink. And now, with 3nm, it is no less different. This was evident in the two classes of 3nm node technology that TSMC spoke about at IEDM, where the original base N3 had an SRAM bitcell size only ~5% smaller than N5, whereas the enhanced variant N3E was the same size as N5. 

The complexities at advanced node processes have accelerated the move towards advanced packaging and chiplets. While TSMC is still betting on FinFet transistors for its 3nm process (as opposed to Samsung, which will move to GAA architecture for 3nm), it has confirmed that it will also move to GAAFET for 2nm chips in 2025. 

Therefore, one is likely to believe that with sticking to FinFet and showing no improvement in SRAM scaling, TSMC has stepped on the wrong foot with its 3nm production. This implies that the cost of implementing the chip on the most advanced process technology is increasingly higher, and, as SemiAnalysis reports, “the fixed costs of implementing a product in the newest process technology are getting so large that it represents a massive risk for companies”.

However, SemiAnalysis’ Dylan Patel told Analytics India Magazine that despite its limitations, TSMC’s 3nm is still the best process technology and many companies will use it, even though it is not perfect—adding that there are some cost improvements plus performance improvements. 

Same sentiment was also shared by Sravan Kundojjala, Principal Industry Analyst at Strategy Analytics, who—while speaking to Analytics India Magazine on the subject—said, “3nm is not insignificant in terms of power savings, performance and area. It is better than 5nm to 4nm transition. It will help CPU, GPU and AI processor companies to improve performance”.

Further, on behalf of Strategy Analytics, Sravan also said, “3nm will see higher success compared to 5nm and 7nm in the first year of the introduction. We think 3nm wafer revenue will account for more than 10% of TSMC’s wafer revenue in 2023. HPC (data center, AI, FPGA, networking etc.) and smartphones (apps processors and basebands) will drive 3nm adoption. We expect that Apple will lead the 3nm adoption in 2023 while Android vendors will jump on 3nm in 2024.”