As AI and IoT Space See A Major Boom, Open Source RISC-V Chips Can Address The Computing Needs

Dr. Krste Asanovic at RISC-V Tech Symposium in Bengaluru

SiFive and Open-Silicon, two global giants of the semiconductor industry hosted Bangalore’s first RISC-V Tech Symposium. Attended by industry leaders and dignitaries such as Vivek Tyagi, Director, Western Digital; Chandan Haldar, CEO, Morphing Machines; Dr. Krste Asanovic, Chairman of RISC-V Foundation and Co-Founder and Chief Architect of SiFive, and Shafy Eltoukhy, SVP and General Manager, Open-Silicon, among others, it aimed to highlight the use cases on RISC-V, its impact on the semiconductor industry and how it can further processor innovation through open standard collaboration.

Developed by the University of California in 2010, RISC-V is an open ISA (Instruction Set Architecture) and RISC-V based chips could be the next game changer in the AI and IoT market. At a time when chip architecture has received renewed interest from a spate of startups and leading chipmakers like Intel, AMD, the open instruction set architecture based RISC-V can disrupt the market significantly.

RISC-V based chips are increasingly being preferred by semiconductor companies, chip design organisations, startups and governments across the globe to deliver solutions in a fast and efficient manner. As the speakers discussed the nuances of standardisation of RISC-V ISA for all computing devices, they also provided impetus on AI as the next revolution in digital world, innovation for a data-centric world, high bandwidth memory IP subsystem and RISC- V as a game changer for startups.


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For instance, India has already adopted RISC-V as national ISA, whereas Israel Innovation Authority is creating GenPro platform around RISC-V. There are many other governments at various stages of  adoption.

“The semiconductor ecosystem has long been hindered by increasing costs, limited access to IP architectures and an inability to customize,” said Sunil Shenoy, VP of Hardware Engineering of SiFive. “RISC-V, as an open ISA and move to layered approach of SoC Design has the capacity to unleash a whole new era of hardware innovations because it democratizes access to all inventors, from major corporations, startups and research institutes to students and enthusiasts.”

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Speaking at the event, Vivek Tyagi of Western Digital shared that as machine learning, AI and IoT space grows, there is a need to support the computing needs of these growing markets as general purpose chips will not be able to deliver performance required for these kind of applications and deal with huge numbers of data. “20 years from now, data was just a record but over the years it has been extensively used to improve efficiency. As the role of data is evolving, how we store it and monetise it are some of the pressing challenges the industry faces. There is a need for specialised architecture and that is where we are adopting RISC-V,” he said.  

It is being deployed in various processes such as NAND controller SoC which is a multi-purpose SoC for consumer SSD applications. Some of the advantages of using RISC-V, as pointed out by Tyagi are full advantage of open source software ecosystem, instruction optimisation for NAND media handling and freedom of power and performance optimisation for end applications. He further stressed that RISC-V is enabling companies to build applications and processes as per their need.“Just like the rapid adoption of open source projects in the past, RISC-V will also witness massive adoption in the future”, he said, on a concluding note.

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Srishti Deoras
Srishti currently works as Associate Editor at Analytics India Magazine. When not covering the analytics news, editing and writing articles, she could be found reading or capturing thoughts into pictures.

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