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Building a Fault-Tolerant Quantum Computer, The Amazon Way

Building a Fault-Tolerant Quantum Computer, The Amazon Way

  • The active quantum error correction is an approach for reducing gate error rates by redundantly encoding information into a protected qubit using various physical qubits.

Recently, a team from AWS Center for Quantum Computing released its first architecture paper that described the process of building a fault-tolerant quantum computer with a novel approach to quantum error correction (QEC). 

The researchers presented a comprehensive architectural analysis for a fault-tolerant quantum computer based on cat codes concatenated with outer quantum error-correcting codes. The research delved deep into a few scientific details of building larger and more useful quantum computers. 

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Quantum algorithms can resolve complex practical problems in various areas, including medicine discovery, designing new materials, and optimising financial portfolios and logistics processes. Building a fault-tolerant quantum computer is one of the complex scientific challenges of the 21st century.

A successful quantum computing architecture has to meet multiple complex criteria. For instance, it must have a threshold error rate achievable by hardware on a large scale, a convenient physical layout, and a low overhead for fault-tolerant algorithms. At present, most quantum computing systems have qubits, the most basic unit of quantum information. 

However, qubits are highly unstable and tend to collapse from their quantum state in the outside environment. 

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“The quantum algorithms that are known to be useful, those that are likely to have an overwhelming advantage over classical algorithms may require millions as well as billions of quantum gates. However, quantum gates, which are the building blocks of quantum algorithms are prone to errors and such errors can accumulate to spoil the result of complex computations,” the researchers said.

The tech behind

Recent studies have shown that qubits with highly biased noise are a promising route to fault tolerance, at least when gates that preserve the noise bias can be easily implemented in the architecture.

According to the researchers, one possible route to realising such qubits is via two-component cat code, a bosonic qubit encoded in an oscillator mode, subjected to engineered two-photon dissipation or engineered Kerr non-linearity. This engineered interaction heavily suppresses the population transfer between the two constituent coherent states of the cat qubit, causing an effective noise bias towards phase-flip errors on the encoded logical qubits. Therefore, concatenating the cat code with another quantum error-correcting code can be done efficiently by tailoring the outer code to suppress the dominant phase-flip errors. The researchers termed these coding schemes as the concatenated cat codes. 

The research provides a full-stack analysis of a fault-tolerant quantum architecture based on cat codes concatenated with outer quantum error-correcting codes. The analysis has been broadly classified into three categories: 

1) A hardware proposal 

2) A physical-layer analysis of gate and measurements errors and 

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3) A logical-level analysis of memory and computation failure rates.

For the architecture, the researchers used a combination of active QEC and passive or autonomous QEC. The active quantum error correction is an approach for reducing gate error rates by redundantly encoding information into a protected qubit using various physical qubits. This allows the researchers to detect and correct errors. It also allows the implementation of gate operations on the encoded qubits in a fault-tolerant way.    

While the passive or autonomous quantum error correction (QEC) is a contrasting approach, it needs a physical computing system with inherent stability against the errors. The cat qubit encoding can suppress the bit-flip errors, while the remaining errors are taken care of by active quantum error correction built on top of the cat qubits.

Contributions 

  • The researchers presented a comprehensive architectural analysis for a fault-tolerant quantum computer based on cat codes concatenated with outer quantum error-correcting codes.
  • They proposed a system of acoustic resonators coupled to superconducting circuits with a two-dimensional layout for the physical hardware.
  • Using estimated near-term physical parameters for electro-acoustic systems, the researchers performed a detailed error analysis of measurements and gates, including CNOT and Toffoli gates.
  • The researchers obtained realistic full-resource estimates of the physical error rates and overheads needed to run practical fault-tolerant quantum algorithms.

Wrapping up

The AWS Center for Quantum Computing paper describes a way to build a large-scale processor based on cat qubits, substantiated by simulations spanning from the component level up to the system level. The researchers found that with around 1,000 superconducting circuit components, one could construct a fault-tolerant quantum computer that can run circuits intractable for classical supercomputers. Also, hardware with 32,000 superconducting circuit components could simulate the Hubbard model in a regime beyond the reach of classical computing.

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