Intel has unveiled a roadmap to make up lost ground in the chip manufacturing industry. The chip giant intends to accelerate its investments and drive innovation to power Intel through 2025 and beyond.
Intel has unpacked its new node names and the innovations enabling each node. The rationale behind the decision is to align the naming and numbering systems with the rest of the industry. For decades, the process node names corresponded to the real length of physical transistors, and Intel still continues to follow the pattern, although the naming and numbering schemes used by the rest of the industry no longer refer to any specific measurement but rather as a label to describe technology. The new node naming is based on technical parameters for a lucid framework that gives an accurate view of process nodes.
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Intel 7: Previously named 10nm Enhanced Superfin, the node will deliver a 10 to 15 percent performance per watt increase compared to its predecessor (10nm Superfin). Intel 7 will be used in products like Alder Lake chips and Sapphire Rapids for data centers.
Intel 4: Previously Intel 7nm, the node fully embraces EUV lithography–something already utilised by Samsung and TSMC’s 5nm nodes. The node will use the same FinFET transistor architecture that Intel has been operating since 2011. With a 20 per cent performance per watt increase and other improvements, it will go into production by the second half of 2022.
Intel 3: Intel 3 will deliver an 18 percent performance per watt increase using FinFET optimisations and increased EUV over Intel 4. It leverages and implements a denser, high-performance library and increased intrinsic drive current, among other improvements. Intel 3 will be rolled out in the second half of 2023.
Intel 20A (Angstrom Era): By 2024, Intel intends to enter something it calls the ‘Angstrom Era’ with its two new technologies RibbonFET and PowerVia. After FinFET in 2011, RibbonFET will implement gate-all-around transistor architecture. PowerVia is Intel’s interconnect innovation and industry-first implementation of backside power delivery providing signal routing.
Along with the process roadmap, Intel also introduced its new IDM 2.0 strategy. In addition, the company announced two major updates to Feveros chip-stacking packaging technologies. Feveros Omni will allow more diversity in stacked chips, and Feveros Direct will enable direct copper to copper bonding between components which will minimise resistance and decrease bump pitches. The new updates are planned for 2023 production.
“Moore’s Law is alive and well. We have a clear path for the next decade of innovation to go to ‘1’ and well beyond. I like to say that, until the periodic table is exhausted, Moore’s Law isn’t over, and we will be relentless in our path to innovate with the magic of silicon,” Pat Gelsinger, Intel CEO, stated.
Embedded multi-die interconnect bridge (EMIB) as the first 2.5 D embedded bridge solution is still in place since 2017. Sapphire Rapids will be the first Xeon datacenter product to ship in volume with EMIB. It will also be the first dual-reticle-sized device in the industry, delivering nearly the same performance as a monolithic design. Beyond Sapphire Rapids, the next generation of EMIB will move from a 55-micron bump pitch to 45 microns. AWS will be Intel’s first customer to use and provide insights into the IFS packaging.
Intel’s ambitious roadmap might be of help to the company to rearrange and recontextualise its products against competition including AMD, Nvidia and Qualcomm. Apple’s M1 Macs, for example, use superior 5nm chips from TMSC already and outperform Intel’s products.