Intel hosted Architecture Day last week. At the third edition of its annual affair, the chip manufacturing giant disclosed several architectural innovations at work. This event saw the company demonstrating some of the products they have been working on, which signify Intel’s biggest shift in Intel architectures in a generation, claimed Raja Koduri, senior VP and general manager at Intel.
“The breakthroughs we disclosed today also demonstrate how architecture will satisfy the crushing demand for more compute performance as workloads from the desktop to the data centre become larger, more complex, and more diverse than ever,” Koduri said.
Here we detail some of the major announcements made at the event.
Code-named Gracemont, the company’s new x86 Efficient core, would address compute requirements across the entire spectrum of customer needs. In addition, Intel aims to make it the world’s most efficient x86 CPU code. Compared to Intel’s most prolific CPU microarchitecture, Skylake, Efficient cores deliver 40 per cent more single-threaded performance at the same power. Further, Efficient-cores deliver 80 per cent better performance while consuming less power than two Skylake cores running four threads.
This x86 core is the highest performing CPU core from Intel, Koduri claimed. “It also delivers a step function in CPU architecture performance that will drive the next decade of compute,” he further added. It is designed to have a wider, deeper, and smarter architecture that can fit in more parallelism, increase execution parallelism, increase performance, and reduce latency. Performance-core provides 19 per cent Geomean improvement and can support large data and code footprint applications.
Performance-core has dedicated hardware, including new Advanced Matrix Extensions (AMX); it is best for machine learning applications as it offers an 8x increase in artificial intelligence acceleration.
The company has been teasing the features of Alder Lake since last year’s Architecture Day. As per the announcement at this year’s event, Alder Lake will be Intel’s first performance hybrid architecture with the new Intel Thread Director. It is the first chip from Intel, based on its Intel 7 Technology which uses the same tech as the company’s current 10nm technology. Alder Lake will offer a mix of both performance and efficiency of x86 cores. Products based on Alder Lake will start shipping this year.
One of the major roadblocks that Intel has faced regarding its hybrid processor architecture designs is managing multiple threads most efficiently. Additional analysis is required when there are two cores of different performance and efficiency. To remediate this, Intel has announced Thread Director. It is a unique approach for scheduling that ensures Efficient-cores and Performance-cores work together in intelligently assigning workloads from the beginning and optimising the system for superior real-world performance. The Thread Director is built directly into the core, and it works with the operating system to place the right thread at the right time.
Ponte Vecchio and Alchemist SoCs
Ponte Vecchio is, by Intel’s admission, a more complex SoC. It is enabled by Intel’s open, standard-based, cross-architecture unified software stack, OneAPI and built on technologies such as Intel’s advanced semiconductor processors, EMIB technology, and Foveros 3D packaging. With Ponte Vecchio, Intel is introducing the 100 billion-transistor device that delivers industry-leading FLOPs and compute density to carry out applications on artificial intelligence, high-performance computing, and advanced analytics workload. Further, Ponte Vecchio has broken the industry record of inference and training throughput on a popular AI benchmark.
Another major SoC announced at the event was Xe HPG-based Alchemist SoCs (formerly code-named DG2). In addition, Intel announced Xe HPG, a new discrete graphics microarchitecture designed for gaming and creation workloads.
The introduction of Sapphire Rapids for next-generation data processors was among other announcements. It combines Intel’s Performance-cores with new accelerator engines and consists of a tiled SoC architecture. Its USP is that it can deliver significant scalability while offering the benefits of a monolithic CPU.
Intel also introduced Mount Evans, its first dedicated ASIC-based infrastructure processing unit (IPU), and Oak Springs Canyon, a new FPGA-based IPU-based architecture.
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I am a journalist with a postgraduate degree in computer network engineering. When not reading or writing, one can find me doodling away to my heart’s content.