IISc develops design framework for next generation analog chipsets for AI applications

Indian Institute of Science (IISc) researchers have developed a design framework to build next-generation analog computing chipsets. Using this design framework, they have built a prototype of an analog chipset called ARYABHAT-1 (Analog Reconfigurable technologY And Bias-scalable Hardware for AI Tasks). IISc said that this type of chipset could be very helpful for AI-based applications such as object or speech recognition and those that require massive parallel computing operations at high speeds..

The researchers have outlined their findings in two pre-print studies (presently under peer review). They have also filed patents and intend to work with industry partners to commercialise the technology.

Image: IISc

Most electronic devices use digital chips because the design process is simple and scalable. Chetan Singh Thakur, Assistant Professor at the Department of Electronic Systems Engineering (DESE), IISc, said that the advantage of using analog is massive, especially in terms of power usage and size.

IISc states some difficulties associated with analog processors:

• Testing and co-design analog processors are difficult.
• Analog chips don’t scale easily. So, they have to be individually customised while transitioning to the next generation technology or to a new application. This makes their design expensive. 
• The trade-off between precision and speed with power and area is not easy when it comes to analog design.

The researchers said that different machine learning architectures can be programmed on ARYABHAT and can operate robustly across a wide range of temperatures. The architecture is also “bias-scalable.” Its performance remains the same when the conditions like voltage or current are modified.