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Memory Architecture Sees Advancement Owing To Research By IIT Guwahati
Memory Architecture Sees Advancement Owing To Research By IIT Guwahati

Memory Architecture Sees Advancement Owing To Research By IIT Guwahati

The research is led by Prof. Hemangee K. Kapoor, Sukarn Agarwal, Palash Das, Sheel Sindhu Manohar, Arijit Nath and Khushboo Rani.

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Key takeaways

  • IIT Guwahati researchers have advanced memory architectures in multi-core processor systems by reducing data redundancy.
  • Improvements in memory access patterns help prevent wear-out in frequently written locations.
  • The introduction of hybrid memory structures allows for efficient handling of slow writes, protecting non-volatile memory.
  • Future research aims to address challenges related to memory lifetime and encryption methods.
5 min

Researchers from the Indian Institute of Technology, Guwahati, have made contributions to memory architectures by preventing redundancy in data values and improving slow and frequent writes in multi-core processor systems. 

Specific contributions, being in multi-core processor-based systems that need an equally large on-chip memory to commensurate the data demands of the ever-growing applications, and hence preventing energy consumption to ensure the temperature, remains under the thermal design power (TDP) budget.  

“The application data access patterns are not uniformly distributed and hence lead to several orders of writes to certain memory locations compared to others. Such heavily written locations become prone to wear-out and thus prevent the use of the complete memory device without error corrections,” said Prof. Hemangee K. Kapoor, Department of CSE, IIT Guwahati, while explaining the challenges of multi-core processor-based systems.

To handle this non-uniformity, researchers developed methods to evenly distribute the accesses across the overall memory capacity to reduce the wear-out pressure on heavily written locations and worked in the area, which avoids writing redundant values, thus prolonging the wear-out.  

“Slow and frequent writes can be redirected to temporary SRAM partitions sparing the NVM from getting written with such frequent accesses. Such structures are called hybrid memories. The team is also working on extending them to off-chip main memory. The future challenges are to handle lifetime enhancement in the presence of encryption methods used to secure the non-volatile memory and to handle temperature and process technology-driven disturbance errors introduced when the cells are read or written,” she added.

The research is being led by Prof. Hemangee K. Kapoor, Department of Computer Science and Engineering (CSE), IIT Guwahati, and comprises a team of research scholars: Sukarn Agarwal, Palash Das, Sheel Sindhu Manohar, Arijit Nath and Khushboo Rani. 

The findings of their research can be found here.

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