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New Cadence App Boosts AI Chip Power Modelling with NVIDIA with 97% Accuracy
New Cadence App Boosts AI Chip Power Modelling with NVIDIA with 97% Accuracy
Chip Off the Old Block

New Cadence App Boosts AI Chip Power Modelling with NVIDIA with 97% Accuracy

The app allows engineers to track power estimation, reduction and sign-off through the design process.

Published Updated

Key takeaways

  • Cadence's new Dynamic Power Analysis app achieves 97% accuracy in AI chip power modeling.
  • Engineers can analyze billion-gate chip designs in just two to three hours.
  • The app reduces risks of over or under-designed semiconductors before final production.
  • Integration into existing workflows enhances efficiency in AI, ML, and GPU systems.
  • The collaboration with NVIDIA drives transformative technology for semiconductor developers.
5 min

Cadence Design Systems, a long-standing heavyweight in computational software, has developed a new power analysis technology through its long-standing collaboration with NVIDIA. 

The solution allows engineers to analyse billion-gate AI and machine learning chip designs within hours, with up to 97% accuracy.

The new Dynamic Power Analysis (DPA) app runs on the Cadence Palladium Z3 Enterprise Emulation Platform. It helps semiconductor and systems developers predict energy use across billions of cycles, a task that conventional tools could not scale to without impractical timelines.

“Cadence and NVIDIA are building on our long history of introducing transformative technologies developed through deep collaboration,” said Dhiraj Goswami, corporate vice president and general manager of HSV at Cadence. “This project redefined boundaries, processing billions of cycles in as few as two to three hours.”

The Palladium DPA app enables developers to test power usage under real workloads before tapeout, when designs can still be optimised. This approach aims to reduce risks of over or under-designed semiconductors while ensuring efficiency in AI, ML and GPU-driven systems. 

Cadence said the app integrates into its more exhaustive analysis and implementation solutions, allowing engineers to track power estimation, reduction and sign-off through the design process.

Narendra Konda, vice president of hardware engineering at NVIDIA, said, “By combining NVIDIA’s accelerated computing expertise with Cadence’s EDA leadership, we’re advancing hardware-accelerated power profiling to enable more precise efficiency in accelerated computing platforms.”

In an exclusive interview with AIM in April, Jayashankar Narayanankutty, the group director at Cadence, also discussed the company’s expanding digital twin strategy and its implications across sectors.

“At Cadence, we didn’t set out to do this, but over time, our ability to simulate billions of nodes simultaneously evolved into something far more powerful,” Narayanankutty said. “That’s what led us into digital twins, and the results have been nothing short of groundbreaking.”

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