Rajeev Chandrasekhar Inaugurates Synopsys’ Chip Design Centre in Noida

Union Minister of State for Electronics and IT, Rajeev Chandrasekhar, inaugurated Synopsys’ Chip Design Centre at DLF Tech Park in Noida today. As Synopsys’ second-largest design centre in India, it houses approximately 6,000 Indian engineers, constituting 27% of the global design workforce. 

These engineers contribute to every aspect of the design cycle of semiconductor chips/IP Cores, reaffirming India's growing influence in fabless chip design and innovation.

Minister Chandrasekhar spoke about the evolving ecosystem of fabless chip design and innovation in India during the inauguration. He commended Synopsys for its significant contribution to this ecosystem, emphasising the importance of design in India as outlined by Prime Minister Modi. 

The minister's initiatives, including SemiconIndia futureDESIGN, Digital India RISC-V (DIR-V) Program, and the India Semiconductor Research Center (ISRC), align with the vision that "Design in India is as crucial as Make in India."

Synopsys' increasing footprint in Noida, hosting 1,650 engineers to begin with, stands as a testament to the expanding ecosystem of fabless chip design and innovation in India. The Indian engineers at Synopsys play a vital role not only in the design cycle of semiconductor chips/IP Cores but also contribute to the success stories of leading semiconductor companies globally. Their expertise in EDA/IP solutions is integral to the development of chips by various companies.

Synopsys, is a global company contributing to $5.9 billion in revenue, is renowned for its design portfolios covering silicon to software. Established in 1986, the company was pivotal in commercialising logic synthesis and revolutionising digital design creation from language descriptions. With a market-leading position in Electronic Design Automation (EDA) tools and Interface, Foundation, & Physical IPs, Synopsys stands at the forefront of advancing digital chips within the technology ecosystem.