Article Complete
AIM
China’s CXMT Claims Memory Breakthrough, Challenging Samsung and SK Hynix
China’s CXMT Claims Memory Breakthrough, Challenging Samsung and SK Hynix

China’s CXMT Claims Memory Breakthrough, Challenging Samsung and SK Hynix

The Chinese chipmaker plans to launch server memory based on the new architecture by year-end, following the mass production of its fifth-generation DRAM platform and LPDDR6 chips.

Published Updated

Key takeaways

  • CXMT has developed a new memory-cell architecture that could enhance data density and challenge leading manufacturers.
  • The company plans to introduce server memory based on its innovative 4F² architecture by the end of 2026.
  • CXMT's approach includes a Vertical Surrounding Gate design to minimise electrical leakage and improve manufacturing efficiency.
  • The chipmaker has recently commenced mass production of its fifth-generation DRAM platform and LPDDR6 chips.
  • CXMT's advancements in memory technology may help it close the competitive gap with established South Korean firms.
5 min

ChangXin Memory Technologies (CXMT), China’s largest domestic DRAM maker, claims to have developed a memory-cell architecture that could pack more data into less silicon than existing designs, potentially challenging Samsung Electronics and SK Hynix.

The company plans to launch a new server-memory product based on the 4F² architecture before the end of 2026, CXMT President Cao Kanyu said at a recent industry conference in Shanghai, as reported by Bloomberg.

If the architecture achieves commercially viable production yields, it could narrow the gap with South Korea’s memory manufacturers, which have explored similar designs for years.

Conventional 6F² DRAM architecture uses a memory-cell footprint equivalent to six times the square of the minimum feature size. However, a 4F² design reduces that footprint to four times the square, potentially increasing memory density and lowering manufacturing costs. 

CXMT said it is using a Vertical Surrounding Gate approach that changes how transistors are arranged to reduce electrical leakage and other problems associated with further miniaturisation.

The announcement comes as CXMT advances across several memory categories. 

Last month, the company announced mass production of its fifth-generation DRAM platform, known as G5, and introduced 24-gigabit LPDDR5X chips built on the process. CXMT said the platform achieves an 11.95-nanometre active-area half-pitch and produces at least 50% more dies—single rectangle of silicon—per wafer than its predecessor. 

Earlier that month, CXMT announced mass production of LPDDR6 memory, with the chips making their commercial debut in Xiaomi’s 18 Fold flagship smartphone. The company claims peak data rates of 12,800 megabits per second, alongside up to 60% higher bandwidth and 20% lower power consumption than the previous generation of LPDDR5X, based on its internal testing

CXMT’s progress is putting pressure on an already competitive memory market, where AI data centre demand has driven up prices and pushed manufacturers to expand capacity. 

The company raised approximately $8.6 billion in its July Shanghai IPO, and its share of global DRAM revenue reached 9.5% in the second quarter. However, it still lags behind leading manufacturers like Samsung and SK Hynix in high-bandwidth memory (HBM), which powers AI accelerators.

On October 13, Samsung and SK Hynix shares fell more than 7% in South Korea, while Micron also declined in US trading. Bloomberg attributed the sell-off partly to investor reaction to CXMT’s announcement, although concerns about AI investment returns also weighed on semiconductor stocks. 

Membership

Stay ahead with AI insights.

Unlimited access to premium articles, exclusive analysis, and the stories shaping India's AI economy.

Subscribe now

AIM Americas

1190 Miraloma Way Suite P, Sunnyvale, CA 94085

AIM India

1st Floor, Sakti Statesman, Bellandur, Bengaluru – 560103

© 2026 AIM. All rights reserved.