Huawei’s Search for the Next Moore’s Law

Huawei may have unveiled one of its most ambitious semiconductor initiatives yet. The company is proposing an alternative to Moore’s Law, the principle that has guided semiconductor progress for decades.

First articulated by Intel Co-Founder Gordon Moore in 1965, the law held that the number of transistors on a chip doubles roughly every two years, delivering ever-greater performance at ever-lower cost.

At the IEEE International Symposium on Circuits and Systems (ISCAS) held in Shanghai on May 25, Huawei unveiled what it believes could be an alternative path forward—the Tau (τ) Scaling Law.

Rather than relying on traditional geometric scaling, the framework proposes time (τ) scaling as the key driver of semiconductors and electronic systems advancement.

The concept was introduced by He Tingbo, President of Huawei’s Semiconductor Business Unit and Director of Huawei’s Scientist Committee. Among peers and colleagues, the framework has earned the nickname ‘Her’s Law’, in recognition of He’s role in developing it. Often referred to in Chinese tech circles as the ‘chip queen’, He has spent decades helping build Huawei’s semiconductor muscle.

What is Tau’s Law?

The Greek letter tau (τ) is a time constant in circuit theory. In electronics, it represents how quickly a signal can transition from one state to another without getting slowed by resistance and capacitance in the wiring and the device itself, a phenomenon often referred to as RC delay. The smaller the value of τ, the faster and more efficiently a circuit can switch states and process data.

Rather than focusing on shrinking transistor geometries, which have effectively stalled around 7nm in China due to US restrictions on access to EUV lithography, Tau’s Law prioritises shortening signal paths and reducing latency at every level of the computing stack, from transistor circuits to multi-chip systems.

“Geometrical scaling itself has always delivered time domain gain. Faster transistors, shorter response time, higher chip frequencies. This means space and time are two sides of the same coin. Losing geometrical scaling does not mean losing time scaling,” He explained in her keynote.

“We saw time scaling can deliver strong benefits across devices, circuits, chips, and systems.”  

Huawei’s strategy combines multiple technologies, including its LogicFolding design that stacks chip circuits in 3D layers, as well as chiplets and hybrid bonding that connect chips more efficiently. In addition, optical interconnects powered by the Hi-ONE engine and Unified Bus memory fabric help accelerate data movement.

Using these methods, Huawei claims it can achieve 1.4nm-equivalent transistor densities by 2031 without relying on EUV tools.

The company expects to increase hardware integration by more than 100 times by 2035.

Over the past six years, Huawei has developed and mass-produced 381 chips using the Tau Scaling Law, deploying them across a broad range of industries and use cases.

“Necessity is the mother of innovation here. Blocked from accessing ASML’s advanced EUV lithography machines, Huawei is forced to challenge physical constraints to stay relevant in the global AI race,” says Neil Shah, Vice President of Research at Counterpoint Research.

“Huawei’s Tau Scaling Law and LogicFolding approach are being pitched as a post-Moore’s Law alternative. Huawei is focusing on existing equipment, chiplets, 3D packaging, and hybrid-bonding-based 3D folding to stack logic vertically and compress signal travel time,” he adds.

According to Shah, while the architecture offers a potential path beyond traditional transistor scaling, it could also create substantial thermal and packaging challenges that may impact manufacturing yields.

Huawei’s Roadmap 

Huawei’s first major milestone for the technology is expected to be its Kirin processor lineup. Scheduled for release in fall 2026, they will be the first chips to use the LogicFolding architecture. The company is also targeting 1.4-nanometer-class chips by 2031.

To be precise, it will not be 1.4nm in the traditional sense of transistor node sizing—it is an equivalent performance benchmark achieved through 3D stacking and signal-delay compression rather than physical transistor miniaturisation.

Huawei plans to extend the technology to its Ascend AI chips by 2030. 

“We will launch a new Ascend, the full logical folding version with another performance boost,” He said in her keynote.

The Ascend series is central to China’s AI ambitions. Huawei’s Ascend chip series has become increasingly central to powering Chinese AI models, including DeepSeek’s latest flagship model V4, released last month.

“Though Huawei’s race to deploy this inside its flagship Mate 90 series this fall is a highly commendable engineering feat, scaling this to AI data centre will serve as the ultimate litmus test for China’s creative workaround to Western sanctions,” Shah says.

Huawei expects revenue from its AI processors to rise from about $7.5 billion in 2025 to roughly $12 billion in 2026, reflecting around 60% year-over-year growth. The increase is being driven by strong demand from Chinese companies seeking domestic alternatives to NVIDIA’s AI hardware.

IDC data reviewed by Reuters showed that about four million AI accelerator cards were shipped in China in 2025. NVIDIA remained the largest supplier with around 2.2 million units, giving it a 55% market share. Chinese vendors shipped 1.65 million AI chips in 2025, accounting for about 41% of the market. 

Among domestic suppliers, Huawei led with 8,12,000 units, followed by Alibaba’s T-Head with about 2,65,000. Baidu’s Kunlunxin and Cambricon each shipped around 1,16,000 units.

Chip Wars 

Huawei’s τ-scaling initiative is closely tied to the US-China tech rivalry.

Since 2019, US export controls have restricted China’s access to leading-edge chip tools, especially ASML’s EUV lithography systems, while also limiting the ability of companies such as TSMC, Intel and AMD to supply Huawei and other Chinese firms.

As a result, China has faced significant challenges in advancing beyond sub-7nm manufacturing through conventional semiconductor scaling methods.

Meanwhile, Intel is advancing its 18A and 14A processes alongside Foveros packaging. TSMC is moving towards 2nm and expanding its SoIC and 3DFabric technologies, and AMD continues to improve its chiplet strategy and 3D V-Cache designs. 

Despite the geopolitical tensions, He frames Her’s Law as an open invitation rather than a proprietary moat. “No single company can independently find all the answers,” she says, calling for closer collaboration among scientists, engineers and industry peers worldwide to ensure the sustainable development of the electronics industry.