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FPGAs Or ASICs? DARPA Picks Sides In Designing An Unhackable Chip

FPGAs Or ASICs? DARPA Picks Sides In Designing An Unhackable Chip

  • DARPA's SAHARA program aims to automate the conversion of defence-relevant FPGA designs into quantifiably secure Structured ASICs at scale.

The internet, drones, smartwatches and supersonic fighter jets have one thing in common — an electronic chip. In line with Moore’s law, the semiconductor devices have become sleeker and smarter with time. FPGAs, with multiple applications in the defence field, are a good case in point. Meanwhile, 5G wireless, Cloud and storage, AI, and edge applications require a broad range of new equipment, and according to Intel, one size no longer fits all.

FPGA or field programmable gate arrays are expensive to produce and demand more power than the ASIC alternatives. For this reason, America’s Defense Advanced Research Projects Agency (DARPA) has partnered with top chipmaker Intel to develop “unhackable” chips.

Recently, DARPA announced Structured Array Hardware for Automatically Realized Applications (SAHARA) program.

Brief overview of FPGAs 

FPGAs are programmable digital logic chips. All one has to do is use a computer to write a “logic function” or create a text file describing the function. This “logic function” is compiled using software provided by the FPGA vendor that makes a binary file. Finally, one has to connect their computer to the FPGA and download the binary file to the FPGA.

According to Xilinx, ASIC and FPGAs have different value propositions. FPGAs are typically selected for lower speed/complexity/volume design. Today, things have changed. FPGAs have become better, thanks to the rise in logic density and advancement of embedded processors, clocking, and high-speed serial at ever-lower price points. FPGAs have become a go-to solution for almost any type of design.

FPGAs are considered ideal for image processing in aerospace and other defence-related applications due to their programmable nature. But DARPA thinks otherwise. While FPGAs are widely used in military applications today, wrote DARPA, structured ASICs deliver significantly higher performance and lower power consumption, a combination that is critical for efficient and effective alternatives for defence electronic systems.

What’s DARPA upto

Image credits: DARPA

“Intel’s eASIC N5X devices custom logic solutions provide up to 50% lower core power with lower unit-cost compared to FPGAs.” 

DARPA’s SAHARA program aims to automate the conversion of defence-relevant field-programmable gate array (FPGAs) designs into quantifiably secure Structured ASICs at scale.

Though structured ASICs have shown promise, manually converting FPGAs to Structured ASICs is a complex, lengthy, and costly process, according to DARPA. Moreover, conventional conversion processes overlook design security risk. This is where Intel comes on board. The chip giant will help DARPA reduce costs and the time taken for the design process while enhancing chip security. According to DARPA, Intel will share the expertise in automating the conversion process for both currently fielded FPGAs while adding unique chip protection to address supply chain security threats.

According to Brett Hamilton of Microelectronics, the structured ASIC platforms and methods, together with the advanced packaging technology developed in SHIP, will enable the US Department of Defense to more quickly and cost-effectively develop and deploy advanced microelectronic systems.

If project SAHARA goes as per plan, soon we will have chips made with 60 % lesser design time, a 10X reduction in engineering costs, and a 50 percent reduction in power consumption by automating the FPGA-to-Structured ASICs conversion. 

For instance, Intel’s eASIC N5X’s custom logic solutions provide up to 50% lower core power with lower unit cost compared to FPGAs while providing faster time to market and lower non-recurring engineering costs when compared to cell-based ASICs.

Intel claims to be the only player in this space to offer a complete custom logic continuum of FPGAs, structured ASICs, and ASICs to build equipment tailored to unique challenges of time to market (TTM), cost, power, volume, performance, and flexibility requirements.

DARPA’s decision to choose Intel as a partner comes at a time when the latter is shooting for the top spot in the chip space. The company said it would spend nearly $20 billion to establish domestic manufacturing capabilities, of which, Structured ASICs will play a key role. DARPA believes their partnership with Intel will promote in-house foundry capabilities as global chip shortage looms large. 

“The partnership with Intel will ultimately afford the DoD with significant cost and resource savings while enabling the use of leading-edge microelectronics across a host of applications,” said Serge Leef, a program manager in DARPA’s Microsystems Technology Office.

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