Electronic design automation company Cadence Design Systems has launched its ChipStack AI Super Agent, an agentic AI solution for front-end chip design and verification. The company said the tool automates design and verification tasks and delivers up to 10x productivity gains in coding and testing.
“ChipStack represents a major leap in our design for AI and AI for design strategy,” Anirudh Devgan, President and CEO of Cadence, said in a statement. “We are enabling customers to move from months to weeks in critical design and verification tasks.”
The product targets semiconductor design teams that face rising complexity and engineering shortages, according to Cadence. ChipStack is available in early access and has already been deployed with customers, including NVIDIA, Altera, and Tenstorrent.
“As semiconductor complexity continues to accelerate, AI has become essential to designing the next generation of chips,” said Timothy Costa, General Manager of Industrial and Computational Engineering at NVIDIA. He said the collaboration with Cadence improves productivity and efficiency for chip designers.
Arvind Vidyarthi, Senior Director of Engineering at logic devices provider Altera, added that the agent has significantly reduced its verification effort in some areas by approximately 10x. He said the tool helped teams reach closure faster and improve functional coverage on complex designs.
Cadence said the agent automates design and testbench creation, builds test plans, runs regression testing, and supports debugging and issue resolution. The workflow also integrates directly with its electronic design automation tools and AI platforms.
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How the System Works in Practice
“Our customers are facing a significant senior deficit in the engineering talent needed to deliver on their product roadmaps,” said Paul Cunningham, VP and GM of Research and Development at Cadence.
The architecture of ChipStack is built around multiple specialised AI agents rather than a single assistant. These include IP design agents, verification agents, SoC integration agents, debug agents, and sign-off agents, all coordinated through a shared internal control layer. Each agent executes a defined role while accessing the same design context.
A core technical feature is the platform’s use of a structured “mental model” to anchor LLM reasoning in verified design data. The agents connect design sources, generate tests, write code, and provide debug guidance through an end-to-end workflow.
The company said this prevents hallucination by forcing code and test generation to rely on structured facts extracted from specifications and source files, rather than free-form inference. This representation also improves results by enabling agents to reason about relationships among blocks, behaviour, and design intent.
The system supports both on-premises and cloud deployments and can run across different frontier AI models. Cadence said the platform integrates with NVIDIA’s NeMo framework and the NVIDIA Llama Nemotron reasoning model for design and verification workloads.
ChipStack is integrated with Cadence’s existing AI and optimisation stack, including the Verisium verification platform, the Cerebrus intelligent chip exploration system, and the JedAI data and AI platform, which the company said have been used across more than 1,000 tape-outs.
Internally, Cadence places ChipStack at the “agentic workflow” stage of its autonomy roadmap, positioned between complex reasoning systems and fully autonomous chip design.
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