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Gemini Moves into Chip Design with Cadence Collaboration

The collaboration integrates Gemini models with ChipStack AI Super-Agent to improve chip design productivity and deployment on Google Cloud.

Gemini Moves into Chip Design with Cadence Collaboration

Key takeaways

  • Gemini and Cadence have partnered to enhance AI-driven chip design on Google Cloud.
  • The collaboration aims to improve design automation for semiconductor development.
  • ChipStack AI Super-Agent is expected to deliver significant productivity gains in design and verification tasks.
  • The integration supports next-generation semiconductor systems and is available on the Google Cloud Marketplace.
  • Cadence's Mental Model technology enables AI agents to assist in guiding design workflows.

Takeaways drafted with AI from the article text.

The companies will integrate Gemini models with Cadence’s ChipStack AI Super-Agent to support chip design and verification workflows on Google Cloud. The platform is available on the Google Cloud Marketplace and targets design teams working on next-generation semiconductor systems.

The ChipStack AI Super-Agent combines AI-based reasoning with Cadence’s electronic design automation tools. The company said in a statement that the system can deliver up to 10x productivity gains across design and verification tasks, including testbench development, regression management and debug processes.

Paul Cunningham, Senior VP and General Manager at Cadence, said the collaboration marks a step in scaling AI-driven design automation. “By integrating the Cadence ChipStack AI Super-Agent with Gemini, we’re advancing the next generation of agentic design,” he said.

Cadence said the platform uses its Mental Model technology to enable agent-based reasoning. This allows AI agents to guide design workflows while using native EDA tools to improve accuracy and output quality.

The integration also strengthens the connection between Gemini models and Cadence tools. The company said this improves both productivity and the quality of results generated during chip design.

The collaboration uses Google Cloud infrastructure to support compute requirements for AI models and design tools. Cadence said the setup enables a ‘click-to-deploy’ model for chip design workflows on the cloud. This allows teams to deploy and scale design environments without managing infrastructure.

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