QpiAI Builds Real-Time Quantum Error Correction System on Kaveri Processor

Bengaluru’s quantum startup, QpiAI, has developed a quantum error correction system that runs in real time on its 64-qubit Kaveri processor. The platform uses custom hardware and a union-find decoder to reduce latency and enable scalable correction on superconducting qubits.

The system implements a distance-5 rotated surface code using 49 physical qubits, with each decoder instance running on a single chip. It aims to support fault-tolerant quantum computing by correcting errors during computation rather than after it.

The startup launched Kaveri in March last year, with commercial availability expected in the third quarter of 2026, and expectations to help government agencies, research institutions, and businesses alike.

QpiAI Founder Nagendra Nagaraja said the platform aims to demonstrate error reduction and enable fault-tolerant quantum computers (FTQC). He noted that future versions will support new qubit types (Fluxonium variant) and distributed error correction across processors.

“QpiAI FTQC will lead to many advances in pharmaceuticals, chemicals, manufacturing, and climate modelling. QpiAI is excited for this to be demoed soon,” he said.

Nagaraja also revealed to AIM that this is an important milestone for real-time distributed quantum error correction for QpiAI Quantum Supremacy Centre. The centre would yield 10,000 logical qubits once fully operational. 

QpiAI said its decoder achieves an end-to-end latency of about 1.5 microseconds, with a decoding latency of under 1 microsecond. The company compared this with existing systems that operate at around 60 microseconds on CPUs and GPUs.

Vamsi Krishna, VP of Digital Hardware at QpiAI, said the current version will expand to support higher-distance codes and additional configurations. Each correction cycle runs across five rounds of stabiliser measurements to detect qubit and measurement errors. The decoder can complete its task in up to 40 clock cycles and supports parallel operation across multiple logical qubits.

The development aligns with India’s National Quantum Mission, which has supported the design of the Kaveri processor. Abhay Karandikar, Secretary of the Department of Science and Technology, said, “Quantum Error Correction (QEC) is essential for scalable quantum computing.”

He added that implementing QEC in custom hardware “accelerates the deployment” of the 64-qubit system and marks a step towards large-scale quantum use.

The current system uses simulated qubits to validate performance. Integration with physical qubits is under development, alongside work on active correction that adjusts qubits in real time.

QpiAI said its processor design supports surface-code architectures and scalable decoding. The company plans to expand decoder capacity and reduce power use through advanced fabrication.

The development marks a step towards hardware-driven quantum error correction, a requirement for building reliable quantum systems at scale.