OpenAI’s Codex Breakthrough Heralds a New Era in Chip Design

It wasn’t surprising that OpenAI decided to build its own chip. Nearly every major AI lab is trying to control more of the AI stack, from development to deployment. 

What was surprising, however, was OpenAI's claim that Jalapeño, its first custom-built AI chip developed with Broadcom, went from a blank slate to tape-out in just nine months, with significant assistance from its own AI models, including Codex.

The company even claimed that this was the ‘fastest ASIC development cycle ever achieved in high-performance advanced semiconductors.’ 

That suggests AI is beginning to accelerate one of the slowest and most expensive engineering processes in computing.

“OpenAI and Codex are yet another example of this progression, which will, in my opinion, lead to some 80% of chip design being done by AI in the next five years,” Karl Freund, Founder and Principal Analyst at Cambrian AI Research, tells AIM. “This nine-month design cycle will become the norm in the industry in the next three years.” 

OpenAI is unlikely to remain an outlier for long. Meta, Microsoft, Amazon, and Google are already building custom AI chips, while Anthropic is reportedly exploring its own ASIC efforts. 

At the same time, companies such as Cerebras and SambaNova are pushing purpose-built AI processors for training and inference. As more AI-specific chips enter the market, the bigger question may not be who builds the next ASIC, but how AI can accelerate the journey from architecture to silicon.

The New Chipmaking Stack

Experts state that Codex and OpenAI’s internal models likely accelerated Jalapeño’s engineering workflows by helping engineers generate RTL and verification code, automate scripting, debug designs, explore architectural trade-offs, and optimise design iterations.

The speed-up appears to have resulted from compressing the countless engineering and optimisation loops that typically slow ASIC development, while Broadcom’s silicon implementation expertise and established EDA (electronic design automation) toolchains handled the physical design, timing closure, foundry validation, and tape-out (when the design is sent for manufacturing) process. 

One chip design engineer at NVIDIA, who does not wish to be named, tells AIM, “Verification happens to be the bottleneck in chip design, so it is a great target for disruption.”

Modern AI chips contain billions of transistors, and engineers often spend far more time verifying that every part behaves correctly than writing the original design. “Many of its aspects are also amenable to agentic AI, such as writing assertions and testbenches, as well as coordinating various verification tools and approaches,” they add. 

The engineer also notes that OpenAI could speed up design because of its “narrow focus on an AI accelerator with minimum programmability.” “Design time can be improved quite a bit by skipping aggressive optimisations and limiting functionality,” they share. 

However, while AI can act as a productivity layer, the engineer doesn’t see it replacing any of these established EDA tools in the market. 

Agentic EDA 

Parv Sharma, a senior analyst at Counterpoint Research, shares a similar view, noting that Codex serves as an advanced productivity layer on top of the conventional Broadcom stack. “But Codex is not a replacement for Broadcom,” he says. 

Broadcom already develops custom ASICs for customers including Google (TPUs), Meta, and others. The company has also completed multiple tape-outs on the N3 process, giving it firsthand experience with the associated risks. 

“So, a nine-month timeline is enabled due to Broadcom's silicon implementation expertise and OpenAI’s deep software-hardware co-development,” he says. The broader EDA industry has been on the same trajectory.

“The EDA industry is already using AI-powered tools to design. Synopsys and Cadence are using AI across each stage of chip design,” adds Sharma. 

Earlier this year, Siemens introduced its Questa One Agentic Toolkit, saying agentic AI can automate verification planning, debugging, coverage closure, and RTL signoff (verifying hardware description code) while keeping engineers in the loop. Cadence and Synopsys are also embedding AI into their EDA platforms, using it to accelerate chip design, verification, and implementation.

Cadence launched its ChipStack AI Super Agent this year, claiming it can perform tasks that typically consume around 70% of an engineer's time writing and testing design code. The company envisions providing ‘virtual engineers’ rather than just software tools. Early customers include NVIDIA, Altera, and Tenstorrent.

“EDA companies are deploying AI agents to run more compute cycles per design, enabling better outcomes for chip designers and more revenue per customer,” says Sharma. 

In addition, a new wave of startups—including ChipAgents, AllSpice, and Silimate—is building AI-powered tools for semiconductor engineering, ranging from agentic verification and debugging to collaborative hardware design and simulation, signalling growing investor interest in AI-native chip development.

NVIDIA is also increasingly relying on AI internally. 

At NVIDIA GTC 2026, Bill Dally, NVIDIA's Chief Scientist and Senior Vice President of NVIDIA Research, said the company is already using AI across multiple stages of GPU design—from architecture exploration and standard-cell development to debugging and verification. He revealed that NVIDIA’s reinforcement learning-based NB-Cell system reduced a standard-cell library porting task from 80 person-months of engineering effort to an overnight run on a single GPU, while delivering results that matched or exceeded human designs in size, power and delay.

The Future 

Despite AI's growing capabilities, the most critical decisions in chip design will remain human-led.

“Humans will still determine what the chip is intended to do, and what the right tradeoffs should be between cost, performance, and time to market,” says Freund. “Humans will also sign off on a design before tape-out. AI will do the rest.”

Similarly, Sharma says, chip design can be broken down into two buckets. The first one is the rule-based check, like running checks, optimising wire placement across billions of transistors, closing timing budget, simulations and verification. “This is where the AI excels,” he says. 

“Second is judgement-based decisions like deciding what to build (inference vs training, monolith vs chiplet, memory topology etc), analogue mixed-signal design, post-silicon validation. These decisions require context and human input.” 

However, even as AI models are currently only assisting engineers, they may soon be tapped to improve the design process itself.

Just days before OpenAI unveiled Jalapeño, Pushkar Ranade, CTO of Intel Foundry Services, argued on X that the next frontier extends beyond AI-assisted chip design. According to him, AI systems can take high-level objectives, such as latency, power and deployment requirements, and co-design the entire hardware stack, from architecture and memory to manufacturing handoff. 

He also expects every successful tape-out to feed back into these systems, allowing the design process itself to improve over time. 

Over time, AI-designed chips may eventually outperform human-designed chips in ways engineers cannot yet fully explain.