Cadence Partners with TSMC for Advanced AI, Chip Design

Cadence Design Systems has announced a collaboration with TSMC to develop AI-driven design solutions and IP for advanced process nodes and 3D-IC packaging. The partnership aims to speed up chip development for AI and high-performance computing (HPC) applications.

The announcement highlighted that Cadence’s AI design flows now support TSMC’s N2 and A16 technologies, while new silicon-proven IP is available for TSMC N3P. Both companies will also work on EDA (Electronic Design Automation) flow development for TSMC’s A14 process, which is expected to release its first PDK (Process Design Kit) later this year.

Cadence said it has extended its design automation solutions to TSMC’s most advanced process technologies, including N3, N2 and A16. 

Its tools, such as Innovus Implementation System, Tempus Timing Solution and Voltus IC Power Integrity Solution, will help customers optimise power, performance and area for next-generation chips.

“Cadence and TSMC remain committed to speeding up and improving the design process for advanced silicon for our customers,” said Chin-Chi Teng, senior vice president and general manager at Cadence. 

Aveek Sarkar, director of the ecosystem and alliance management division at TSMC, said the company is tackling some of the most complex challenges in semiconductor development to enhance performance and energy efficiency in AI. 

TSMC has validated Cadence’s JedAI and Cerebrus solutions, which include AI-driven features such as automated design rule check violation fixing. These features aim to improve efficiency and shorten design closure times for AI chips on the N2 process.

Cadence’s 3D-IC solutions will now support TSMC’s 3DFabric packaging technologies. New automation capabilities include bump connection management, multi-chiplet physical implementation and smart alignment marker insertion.

On the IP side, Cadence introduced new memory and connectivity solutions built on TSMC's N3P process. These include HBM4 IP, LPDDR6/5X, DDR5 MRDIMM Gen2, PCIe 7.0 and UCIe 32G. Such offerings are designed to address the memory-wall challenge in AI compute systems and enable scalable AI infrastructure.