Article Complete
    AIM

    Keysight Launches 3D Interconnect Designer for Chiplet, 3DIC Design

    Keysight Launches 3D Interconnect Designer for Chiplet, 3DIC Design

    When combined with Chiplet PHY Designer, engineers can also design and optimise 3D interconnects for chiplets and 3D-integrated circuits.

    Keysight Launches 3D Interconnect Designer for Chiplet, 3DIC Design
    Sanjana Gupta··Updated OCTOBER 17, 2026, 12:32 AM
    5 min

    Keysight Technologies introduced 3D Interconnect Designer, a new tool in its electronic design automation (EDA) portfolio. This is to address the growing complexity of 3D interconnect design for chiplet and 3D-IC advanced packages used in AI infrastructure and data centres. 

    The company said the solution automates complex workflows that often delay product development. The tool targets engineers working on multi-die and stacked-die applications, where manual optimisation of vias, transmission lines, solder balls, and micro-bumps slows progress and increases design spins. 

    Nilesh Kamdar, General Manager, EDA Design and Verification at Keysight, said manual 3D interconnect design has become a bottleneck due to rising complexity. 

    “By streamlining the process and providing early insights into potential issues like signal and power integrity, we're enabling engineers to get products to market faster and deliver compliant designs on tighter timelines,” he added.

    Keysight said the software reduces iterations and shortens development cycles by enabling faster design, optimisation and validation of 3D interconnects.

    As chiplet architectures gain adoption, traditional workflows struggle to handle the complexity of 3D interconnect geometries. Engineering teams spend significant time ensuring signal and power integrity in dense systems, which can delay launches and raise costs.

    Keysight said its EDA software provides a dedicated workflow for designing and optimising 3D interconnects accurately. The tool supports complex geometries, such as hatched or waffled ground planes, which help address fabrication constraints in silicon processes, including interposers and bridges.

    The company said the solution accelerates design cycles by removing manual steps and improving first-pass success. It also validates designs against standards such as Universal Chiplet Interconnect Express and Bunch of Wires early in the lifecycle, reducing the risk of late-stage failures. Electromagnetic simulation enables electrical analysis of printed circuit boards and 3D interconnect designs for packages.

    The solution integrates with Keysight’s EDA tools and also supports a standalone version. Teams can incorporate 3D interconnect design and optimisation into existing workflows without major changes.

    When combined with Chiplet PHY Designer, engineers can also design and optimise 3D interconnects for chiplets and 3D-integrated circuits, improving accuracy in multi-die systems.



    Your reaction

    Discussion

    What's your take on this story?

    0/1000

    No comments yet — be the first to share your view.

    Explore our newsletters

    Build your routine with some of our top newsletters or view them all here.

    Wake up informed

    Make sense of the day's AI news and breakthroughs with our morning briefing.

    Belamy
    WeeklyBelamySee the latest

    Industry intelligence

    Receive a roundup of AI adoption stories by industry vertical, curated for professionals.

    3x WeeklySector6See the latest

    By signing up, you agree to our Privacy Policy.

    Membership

    Stay ahead with AI insights.

    Unlimited access to premium articles, exclusive analysis, and the stories shaping India's AI economy.

    Subscribe now

    AIM Americas

    1190 Miraloma Way Suite P, Sunnyvale, CA 94085

    AIM India

    1st Floor, Sakti Statesman, Bellandur, Bengaluru – 560103

    © 2026 AIM. All rights reserved.