Tattvam AI Exits Stealth, Raises $1.7 Mn to Automate Chip Design

London-based semiconductor startup Tattvam AI has announced that it raised $1.7 million in pre-seed funding led by Seedcamp to automate semiconductor chip design using AI. EWOR, Entropy Industrial Capital, Concept Ventures, and semiconductor angel Stan Boland also participated in the round.

The startup aims to cut chip development cycles from two to three years to weeks by building AI systems that understand circuit structures and solve design tasks autonomously. The company plans to launch its first product in the coming months while working with partners on next-generation chips.

“Chip design is fundamentally a reasoning problem over an enormous search space,” said Bragadeesh Suresh Babu, CEO and co-founder of Tattvam AI. “We’re building a reasoning model that actually understands circuits from first principles and doing it in a fraction of the time.”

Demand for custom silicon has increased as companies build specialised processors for AI training and inference. Unlike general-purpose chips, these processors target specific workloads and can deliver higher performance with lower power use.

Technology firms and startups are investing in tailored silicon to meet growing computational needs. As AI models expand and sectors such as autonomous vehicles and drug discovery require more computing power, custom chips offer a competitive edge.

However, chip design still involves years of manual work and a limited pool of engineers. Tattvam AI aims to automate key parts of this process and make custom silicon more accessible.

Babu, an IIT Madras alumnus, previously worked at UK-based startups CoMind and Fractile, and turned down an offer to join Google’s TPU team to build Tattvam AI. He started the company with Lannan Jiang, who previously developed chips at ETH Zurich’s research lab.

Stan Boland, former founder and CEO of Icera and Element 14, backed the startup in the funding round. He said Tattvam AI’s approach could speed up the complex, iterative process of chip design and cut timelines from years to weeks.